Staff Design Verification Engineer

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Lattice Semiconductor is seeking a Staff Design Verification Engineer to join the Soft IP team.  This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow.

Accountabilities: 

• Develop comprehensive verification plans, clear metrics and continuously measure progress against the plan throughout the project

• Understand the specifications, use cases and verify design IPs using System Verilog and UVM

• Develop highly flexible and portable testbenches

• Perform Functional coverage, RTL code coverage

• Collaborate with design engineers, IP developers and SW developers to deliver high quality SoC verification on regular cadence.

• Design and develop testbench components such as Universal Verification Components, BFMs and verification tools

• Develop best practices and world class methods for IP verification

• Create and improve verification tools

Required Skills

• At least 9 years Digital Design Verification Related Experience

• Bachelor or Master’s Degree in Computer Science, Computer Engineering, Electronics and Electrical Engineer

• Strong debugging and analyzing skills in complex digital design

• Experience in HDL and HVL Languages and Methodologies

• Experience in ASIC/FPGA/SoC verification or development cycle

• Experience in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa

• Experience in Python, Perl or Shell Scripting, TCL and Make.

• Strong communication, analytical and documentation skills and ability to interface with another groups/site

• Stay up to date on industry trends and direction of verification technology development

• Advanced knowledge of System Verilog and UVM methodology